High capability density
An average of 64.2 across 12 hardware-code evals, 15.0 points above Qwen3.8-27B and above DeepSeek-V4-Pro (63.8); 62.41 on the semiconductor Agent bench, also above DeepSeek-V4-Pro (57.29).
27B
256K context
Natively multimodal, with deep thinking
- Average across 12 hardware-code evals
- 64.2
- Gain over Qwen3.8-27B
- +15.0
- Hardware-code eval questions
- 6,798
PyHDL-Eval 65.8+46.2
Rule2DRC 48.3+43.4
CVDP-static 58.9+15.2
RTLLM-v2 79.1+14.0
NetlistBench 83.8+14.0
ChipBench 50.4+11.3
Pluto 72.4+10.3
VerilogEval-v2 86.8+9.0
CreativEval 79.2+7.5
VHDLBench 76.2+5.3
ArchXBench 53.5+2.8
NotSoTiny 16.1+1.4
Real case: hardware code Q&A, Micius-Flash-Preview vs DeepSeek V4 Pro
ENOdd Clock Divider · Code & Execution
中文奇数分频器 · 代码与执行
Real case: semiconductor knowledge Q&A, Micius-Flash-Preview vs DeepSeek V4 Pro
ENAcross the Coil: 0.7 V or 12.7 V?
中文线圈两端，究竟是 0.7 V 还是 12.7 V？
Today, Zhiman officially releases Micius-Flash-Preview, its flagship LLM for scientific research and complex engineering R&D, with online access and API access open now and model weights to follow.
Micius (墨子) is Zhiman’s LLM series for science and engineering, with semiconductors, a field dense with knowledge, with long engineering chains and highly concentrated professional tools, as its first focus. It is a model that understands engineering, uses tools and delivers: it reads process documents, circuit schematics and chip layouts, generates and debugs RTL and EDA engineering code, and calls KiCad and related EDA toolchains on its own to finish multi-step engineering tasks.
- Context
- 256K
- Architecture
- Natively multimodal
- Reasoning
- Deep thinking mode
- Average coding output*
- ~15K tokens
Low deployment bar
Deploys on a single 48 GB-class professional GPU; the quantized version runs on a 24 GB consumer GPU.
Data stays in your domain
Supports private deployment on enterprise intranets, meeting semiconductor R&D’s strict requirements for design data security.
* The average across 13 semiconductor-related coding benchmarks, including VerilogEval v2, RTLLM v2.0 and ChipBench.
Semiconductor R&D needs results that can be verified
10+major stages from requirements to tape-out
$1M+floor on 7–28nm mask costs · Source
300,000integrated-circuit talent gap · Source
General models lack high-quality semiconductor corpora, hardware-code data and professional tool environments, and the stronger closed models cannot be deployed locally. The industry needs a specialist model that fills in the domain knowledge, operates professional tools and supports private deployment.
Specialist abilities in four directions
Semiconductor knowledge
Answers process, device and circuit questions, reasoning from physical principles.
Chip and circuit code
Generates Verilog, VHDL and EDA scripts that pass compilation and simulation.
Engineering Agent
Completes multi-step tasks on its own in professional tools such as EDA and KiCad.
Multimodal understanding
Understands engineering images: circuit diagrams, schematics, layout screenshots and waveforms.
From 18 knowledge trees to multi-teacher online distillation
Most of Micius’s R&D effort goes into the data flywheel: the team built semiconductor knowledge trees from 10 disciplinary perspectives and 8 industry-and-standards perspectives, then mapped authoritative corpora onto the knowledge nodes, so every training question traces back to a specific source.
In training, seven domain Teachers are first trained on their specialties, then multi-teacher online distillation (MOPD) brings their abilities together into one model. Code and tool-call trajectories are all verified by actually running them in a sandbox, so what the model learns is engineering behaviour that runs and can be verified.
97%+knowledge-node coverage
210K+candidate semiconductor Q&A
7domain Teachers
- Knowledge trees and authoritative corpora
- Data synthesis and cleaning
- 7 domain Teachers
- Multi-teacher online distillation
- Micius-Flash-Preview
Where it leads, and where it still falls short
Semiconductor knowledge and multimodal
Above Qwen3.8-27B on 12 of 13 metrics; the highest of all models evaluated on RFSchemBench overall and CircuitSense, and tied highest on SuperGPQA microelectronics.
Hardware code
Above Qwen3.8-27B on all 12. An average of 64.2, above DeepSeek-V4-Pro (63.8) and close to DeepSeek V4.1 Flash (65.4); GPT 5.6 Sol (72.3) still leads.
General ability
HMMT rises from 81.82 to 87.9; MMLU-Pro is 84.2, below Qwen3.8-27B’s official result of 87.5, and is the part still to close.
Semiconductor knowledge and multimodal8
Zhiman-SemiBench
in-houseSuperGPQA-semi · Overall
SuperGPQA-semi · Microelectronics
RFSchemBench · Overall
RFSchemBench · Dynamic reasoning
RFSchemBench · Component understanding
PCB-Bench (345 questions)
CircuitSense (169 questions)
Hardware and engineering code12
CVDP-static
VerilogEval-v2
RTLLM-v2
ArchXBench
NetlistBench
VHDLBench
Pluto
NotSoTiny
Rule2DRC
PyHDL-Eval
CreativEval
ChipBench
Agent and general ability4
Semiconductor Agent
GameCraft · Total
HMMT
MMLU-Pro
Beyond the numbers, tested on real engineering
Micius Harness is Zhiman’s in-house engineering Agent platform. It connects the model’s industry knowledge, code and tool-calling abilities with professional software such as EDA and KiCad, and with real projects. Engineers state the task in natural language, confirm at key points, and check the source files, waveforms, layouts and rule-check reports one by one. Every task below was completed by Micius on its own.
DEMO 1
RTL-to-GDS chip design
Completes logic synthesis, place and route, timing analysis, and DRC and LVS layout verification on its own, delivering the GDS, the netlist and the verification reports. The whole flow takes about ten-odd hours; the traditional flow usually takes weeks to months.
- 346
- tool calls
- 0
- router DRC violations
- 15 rounds
- of self-correction after errors
DEMO 2
Transistor control board PCB
Starting from component-library search and part selection, Micius generates the schematic and then the PCB in KiCad, completes placement, routing and copper-pour trimming for 9 footprints, and finally exports a 3D render straight from the submitted PCB file. The video replays the actual tool-call record of this task.
- 8
- design stages
- 9
- footprints
- 12
- copper-pour edits
DEMO 3
Chip package design workbench
Taking a WB-PBGA package as the example, it builds package-design software from natural-language requirements and completes an actual design, closing the full loop of “engineering need → purpose-built tool → engineering task”.
DEMO 4
Replicating and merging industrial software
Explores FreeCAD, Calc and Blender on its own and integrates them into new software that models, calculates and renders; change a dimension and the model, the calculation results and the render all update together.
Micius Harness workbench
Engineers talk with the model in one interface while viewing waveforms, layouts, 3D models and run previews.
Chip engineering
Reads the project notes, analyses the waveforms, then interprets the design against the synthesized netlist and the physical layout.
PCB analysis
Opens the board file, summarises its layers and components, then rotates and spreads the layers to inspect them.
CAD mechanical design
Opens a 3D model, measures dimensions directly, sections it to see inside and checks the sketch constraints.
Godot robot scene
Inspects and exports an existing scene, previews it running on the same screen, pauses, single-steps and switches cameras.
Runs on a single GPU, works on your intranet
Local deployment
Supports mainstream inference frameworks such as vLLM, SGLang and Ollama.
| Version | GPU |
|---|---|
| FP8 | 48 GB-class professional GPU |
| 4-bit | 24 GB consumer GPU |
API access
Connect through the Zhiman Open Platform, compatible with the OpenAI and Anthropic interfaces. At public API prices, the cost per token is more than 80% lower than leading closed models, and the overall inference cost of a typical long-chain industrial Agent task is expected to fall by more than 70%.
Weights and tools
Model weights will be released soon; stay tuned. Micius Harness offers a CLI and a desktop workbench; the desktop app supports macOS and Windows.
Iterating in real R&D
A larger Micius model is expected to launch soon. Next, Micius will go into the real R&D flows of chip-design companies and fabs to be tested there, with tape-out results, sign-off reports and engineer reviews as the final measure; failures exposed in real tasks will be traced to specific nodes in the knowledge tree, so iteration is measurable and traceable.